1. Field of the Invention
The present invention concerns a display, and more particularly a tracking control circuit of a display. The display may be a flat panel display.
2. Description of the Related Art
An earlier display displays a digital video signal converted from an analog video signal supplied by a host such as a personal computer system. In this case, the analog video signal from the host is firstly amplified by an amplifier, and converted into the digital video signal through an analog-to-digital converter, which performs sampling operations on the analog video signal in synchronism with a second sampling clock signal. The second sampling clock signal is obtained by properly delaying a first sampling clock signal supplied from a clock generator by means of a tracking control circuit, which adjusts the delaying time according to a tracking control signal supplied from a microcomputer.
The tracking control circuit includes a plurality of buffers for delaying the first sampling clock signal, and a multiplexer for selecting one of the outputs of the buffers to generate the second sampling clock signal according to the tracking control signal.
The microcomputer generates a horizontal synchronizing signal having a particular polarity according to the horizontal synchronizing signal received from the host. For example, if the flat panel display is characteristically operated in synchronism with a synchronizing signal of negative polarity, the microcomputer generates the horizontal synchronizing signal of negative polarity. The clock signal generator generates the first sampling clock signal of the frequency corresponding to the received horizontal synchronizing signal.
The horizontal synchronizing signal supplied from the host has a frequency varying with the display mode, i.e., resolution. The analog video signal is inputted in synchronism with the horizontal synchronizing signal. Hence, the clock signal generator generates the first sampling clock signal having a frequency according to the display mode. The clock signal generator is generally achieved by using a phase locked loop circuit (PLL circuit).
However, although the clock signal generator generates the first sampling clock signal having a proper frequency for the present display mode, it is very difficult for the A/D converter to perform a correct sampling operation on the analog video signal. For the clock signal generator hardly generates the sampling clock signal proper to each display mode. This requires the tracking control.
The tracking control causes the A/D converter to perform a correct sampling operation on the analog video signal to properly reconstruct the original video signal. This is carried out by the tracking control circuit, which delays the first sampling clock signal of the clock signal generator according to the tracking control signal, supplying it to the A/D converter. The tracking control signal is supplied by the microcomputer according to a tracking adjustment key input made by the user.
Such a tracking control circuit employs a plurality of buffers to perform the delay function. However, the buffers vary the delaying time so as to result in improper conversion of the analog video signal to the digital video signal if they are subjected to an external stress, such as heat, which is common to a flat panel display, for example.
The following patents each discloses features in common with the present invention: U.S. Pat. No. 4,757,264 to Lee et al., entitled Sample Clock Signal Generator Circuit, U.S. Pat. No. 4,851,910 to Kawai et al., entitled Synchronizing Pulse Signal Generation Device, U.S. Pat. No. 4,290,022 to Puckette, entitled Digitally Programmable Phase Shifter, U.S. Pat. No. 4,594,516 to Tokumitsu, entitled Sampling Pulse Generator, U.S. Pat. No. 4,223,392 to Lemaire et al., entitled Clock-Signal Generator For A Data-Processing System, U.S. Pat. No. 5,012,239 to Griebeler, entitled High Resolution Position Sensor Circuit, U.S. Pat. No. 4,839,726 to Balopole et al., entitled Video Enhancement Method And System, U.S. Pat. No. 5,475,440 to Kobayashi et al., entitled Digital Time Base Corrector For Video Signal Reproduction, U.S. Pat. No. 5,359,366 to Ubukata et al., entitled Time Base Correction Apparatus, U.S. Pat. No. 4,864,401 to Kawata et al., entitled Synchronization Signal Generator Without Oscillator, U.S. Pat. No. 4,772,937 to Romesburg, entitled Skew Signal Generating Apparatus For Digital TV, U.S. Pat. No. 5,420,895 to Kim, entitled Phase Compensating Circuit, U.S. Pat. No. 4,998,169 to Yoshioka, entitled Flat-Panel Displays Unit For Displaying Image Data From Personal Computer Or The Like, U.S. Pat. No. 5,675,832 to Ikami et al., entitled Delay Generator For Reducing Electromagnetic Interference Having Plurality Of Delay Paths And Selecting One Of The Delay Paths In Consonance With A Register Value, and U.S. Pat. No. 5,663,767 to Rumreich et al., entitled Clock Re-Timing Apparatus With Cascaded Delay Stages.